STLD

PART1

Mid-1 Syllabus

UNIT-1: REVIEW OF NUMBER SYSTEMS and CODES: Representation of numbers of different radix, conversion from one radix to another radix, r-1’s compliments and r’s compliments of signed members. Gray code ,4-bit codes; BCD, Excess-3, 2421, 84-2-1 code etc. Error detection & correction codes: parity checking, even parity, odd parity, Hamming code.

BOOLEAN THEOREMS AND LOGIC OPERATIONS: Boolean theorems, principle of complementation & duality, De-Morgan’s theorems. Logic operations; Basic logic operations -NOT, OR, AND, Universal Logic operations, EX-OR, EX- NOR operations. Standard SOP and POS Forms, NAND-NAND and NOR-NOR realizations, Realization of three level logic circuits. Study the pin diagram and obtain truth table for the following relevant ICs 7400,7402,7404,7408,7432,7486.

UNIT-2: MINIMIZATION TECHNIQUES: Minimization and realization of switching functions using Boolean theorems, K-Map (up to 6 variables) and tabular method (Quine-McCluskey method) with only four variables and single function.

COMBINATIONAL LOGIC CIRCUITS DESIGN: Design of Half adder, full adder, half subtractor, full subtractor, applications of full adders; 4-bit adder-subtractor circuit, BCD adder circuit, Excess 3 adder circuit and carry look-a-head adder circuit, Design code converters using Karnaugh method and draw the complete circuit diagrams

UNIT-3_1:COMBINATIONAL LOGIC CIRCUITS DESIGN USING MSI and LSI: Design of encoder, decoder, multiplexer and de-multiplexers, Implementation of higher order circuits using lower order circuits. Realization of Boolean functions using decoders and multiplexers. Design of Priority encoder, 4-bit digital comparator and seven segment decoders. Study the relevant ICs pin diagrams and their functions 7442,7447,7485,74154.

PART2

Mid-2 Syllabus

UNIT3_2:INTRODUCTION OF PLD’s: PLDs: PROM, PAL, PLA -Basics structures, realization of Boolean functions, Programming table.

UNIT-4:SEQUENTIAL CIRCUITS-I: Classification of sequential circuits (synchronous and asynchronous), operation of NAND & NOR latches and flip-flops; truth tables and excitation tables of RS flip-flop, JK flip-flop, T flip-flop, D flip-flop with reset and clear terminals. Conversion from one flip-flop to another flip- flop. Design of ripple counters, design of synchronous counters, Johnson counter, ring counter. Design of registers- Buffer register, controlled buffer register, shift register, bi-directional shift register, universal shift register. Study the following relevant ICs and their relevant functions 7474,7475,7476,7490,7493,74121.

UNIT-5:SEQUENTIAL CIRCUITS-II: Finite state machine; state diagrams, state tables, reduction of state tables. Analysis of clocked sequential circuits Mealy to Moore conversion and vice-versa. Realization of sequence generator, Design of Clocked Sequential Circuit to detect the given sequence (with overlapping or without overlapping).

PART3

TextBooks and References

TextBooks
1. Switching and Fininte Automata - Kohavi
-GoogleBooks
2. Digital Design- Morris Mano
-PDFLink
-Google Books(Title is different but same content)

References

1. Switching Theory and Logic Design- Anand Kumar
-Google Books
2. Fundamentals of LogicDesign- Charles H Roth Jr
-Google Books
3. Digital Electronics - R.S.Sedha
-Google Books

Number systems

r= Radix= base

Ex: r= 2,8,10,16 are standard number systems.

Radix=number= Number system name; range

r=2 = BINARY; numbers existing in this base are 0,1

r=8= octal; range=0,1,2,3,4,5,6,7

r=10=decimal; range=0,1,2,3,4,5,6,7,8,9

r=16=hexadecimal = 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F

NOTE: in hexadecimal A means 10 in decimal
Like wise, B=11, C=12, D=13, E=14, F=15

Note: if r=4, then numbers in this radix system are 0,1,2,3

Ex2: if r=18, then numbers in this radix system are 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F,G,H

1.0: representation of decimal system(d) in binary(b), hexadecimal(h), octal(o)

d=b=h=o

0=0000=0=0

1=0001=1=1

2=0010=2=2

3=0011=3=3

4=0100=4=4

5=0101=5=5

6=0110=6=6

7=0111=7=7

8=1000=8=10

9=1001=9=11

10=1010=A=12

11=1011=B=13

12=1100=C=14

13=1101=D=15

14=1110=E=16

15=1111=F=17

16=10000=10=20

17=10001=11=21

Note: since octal has numbers 0 to 7, the binary equivalent have only THREE bits.

ex: 0 in octal has binary equivalent 000

octal= binary

0=000

1=001

2=010

3=011

4=100

5=101

6=110

7=111

Number systems: Conversions

1.1.1: conversion of any radix to decimal

Ex1: (24.16)₈= (________)₁₀

Sol:

= 4×8⁰+ 2×8¹ + 1×8-¹ + 6×8-²

= 20.21875

Answer: (24.16)₈ = (20.21875)₁₀

----------------------------------------------------------

Ex2: (1011.0010)₂= (________)₁₀

Sol:

= 1×2⁰ + 1×2¹ + 0×2²+ 1×2³ + 0×2-¹ + 0×2-² + 1×2-³ + 0×2‐⁴

= 11.125

Answer: (1011.0010)₂ = (11.125)₁₀

----------------------------------------------------------

Ex3: (3AB.52E)₁₆ = (________)₁₀

Sol:

= B×16⁰ + A×16¹+ 3×16² + 5×16-¹ + 2×16-² + E×16-³

=11×16⁰ + 10×16¹+ 3×16² + 5×16-¹ + 2×16-² + 14×16-³

=939.3237305

Answer: (3AB.52E)₁₆ = (939.3237)₁₀

1.1.2: conversion of decimal to any radix

Ex1: (24)₁₀ = (_________)₂

sol:

Divide the given number successively and note down the remainder every time. Because the radix to find is, r= 2, so divide successively given number(here in this example it is 24) by 2.

2 | 24

12- 0

6 - 0

3 - 0

1 - 1

The binary equivalent ( write remainders from bottom to top) is 11000

Answer: (24)₁₀ = (11000)₂

----------------------------------------------------------

Ex2: (17.45)₁₀ = (_________)₂

Sol:

2 | 17

8 - 1

4 - 0

2 - 0

1 - 0

The integer part is 10001

The fractional part is pending.

Now to find the fraction part: successively multiply the fraction part obtained, after multiplying with required radix (here r=2)

0.45 × 2= 0.90

0.90 × 2= 1.80

0.8 × 2= 1.6

0.6 ×2 = 1.2

0.2 × 2= 0.4

0.4 × 2= 0.8

The fractional part (write the integer part of each fraction from top to bottom) is: .011100

Answer: (17.45)₁₀= (10001.011100)₂ = (10001.0111)₂

1.1.3: conversion of (r=2,8,16) to r=(2,8,16)

Ex1: (146.23)₈ = (_______)₂ = (_______)₁₆

Sol:

1 4 6 2 3

001 100 110 010 011

Answer is: (001100110.010011)₂

Now to get Answer in radix_16, group binary numbers as follows:

As radix_16 has 15(F) as highest number, it's binary equivalent is 1111. So four bit representation here.

Group integer part from right to left 4 bits each, the fractional part from left to right 4 bits each. Then write hexadecimal equivalent.

(001100110.010011)₂

0 0110 0110. 0100 11

0000 0110 0110. 0100 1100

0 6 6 . 4 12

0 6 6 . 4 C

Answer is (066.4C)₁₆

----------------------------------------------------------

Ex2: (110001.110)₂ = (__________)₁₆ =(______)₈

Sol:

As radix_16 has 15(F) as highest number, it's binary equivalent is 1111. So four bit representation here.

Group integer part from right to left 4 bits each, the fractional part from left to right 4 bits each. Then write hexadecimal equivalent.

110001.110

11 0001. 1100

0011 0001. 1100

3 1 . C

Answer is: (31.C)₁₆

Now to convert binary to octal, group three bits from decimal point (for integer: right to left; for fraction part left to right)

110001.110

110 001. 110

6 1 . 6

61.6

Answer is (61.6)₈

----------------------------------------------------------

Ex3: (12.5D)₁₆ = (_______)₂ = (_______)₈

Sol:

1 2 . 5 D

0001 0010 . 0101 1101

00010010.01011101

Answer is: (00010010.01011101)₂

now to convert above binary to octal: (group three bits from decimal point)

00010010.01011101

00 010 010 . 010 111 01

000 010 010 . 010 111 010

0 2 2 . 2 7 2

Answer is: (22.272)₈

Boolean Algebra

In STLD course, unless specifically said addition, + symbol is always OR logic only

A, B, C, a, b, c, x, y, z,.... are called Variables or Literals

Boolean Algebra basics:

. is an AND logic

Ex: A.B (sometimes written as AB )

+ is an OR logic

Ex: A+B

' is NOT logic

Ex: B'

Axioms (Postulates): <these don't have proofs>

AND Logic:
0.0=0
0.1=0
1.0=0
1.1=1
OR Logic:
0+0=0
0+1=1
1+0=1
1+1=1
NOT Logic:
0'=1
1'=0

Boolean Theorems: <these have proofs. These use the postulates/axioms>

A+1 =1
Proof: let A=0;
0+1 =1
its proved as per postulate
Also
Let A=1, then
1+1=1; its proved as per postulate.

Similarly, prove the below theorems:

A+0 =A;

A . 1=A

A . 0 = 0

A + A' = 1

A . A' = 0

Commutative law: A+B=B+A

Associative law: A+(B+C)= (A+B)+C

Distributive Law: A(B+C)=AB+AC

Absorption law: A+AB= A
Proof:
A+AB
=A(1+B)
(above theorem, its proved as 1+A=1, so 1+B=1)
=A.1
=A

Redundant law: A+A'B = A+B
Proof:
A+B
= A+ 1.B
=A+(A+A').B
= A+ AB+A'B
=A+AB+A'B
(as per Absorption law A+AB=A)
=A+A'B
Hence proved.

Idempotent law: A.A=A

Consensus Theorem: AB+A'C+BC= AB+A'C
Proof:AB+A'C+BC
=AB+A'C+BC.1
=AB+A'C+BC.(A+A')
=AB+A'C+ABC+A'BC
=AB+A'C+ABC+A'BC

= AB (1+C) + A'C (1+B)
=AB+ A'C
Hence proved.

Demorgans Theorem: (A+B)' =A' B' ; (AB)' =A'+B'

Duality:

Shortcuts are:
. <--------> +
0 <--------> 1
A <--------> A
A'<------>A'

Examples:

1. Dual of 0+0= 0 <------> 1.1=1

2. 1.0 = 0 <--dual---> 0+1=1

3. A+A'=1 <---dual---> A.A' =0

4. A+B' <---dual---> A.B'

SOP = Sum of Products

Ex: AB+ CD

AB is a product term

CD is a product term

Finally Sum of two product terms here, i.e. SOP

POS = Product of Sums

Ex: (A+B).(C+D)

A+B is a Sum

C+D is a Sum

Finally product of two Sums, i.e. POS

f(A,B,C)= Σm (0,4,6,7) is a SOP (Sum of Products)

note: 1. f is a output function representing input literals (or variables) A, B and C.

2. Σ means SOP

3. m means minterms. Here the minterms are 0, 4, 6 and 7

So Σm(0,4,6,7) means SOP with minterms 0,4,6,7.

f(A,B,C)= ΠM (1,2,3,5) is a POS (Product of Sums)

note: 1. f is a output function representing input literals (or variables) A, B and C.

2. Π means SOP

3. M means Maxterms. Here the Maxterms are 1, 2, 3 and 5

So ΠM (1,2,3,5) means POS with Maxterms 1,2,3,5.

Assignment-1

UNIT-1:

1a. A receiver with even parity hamming code is received the data as 1110110. Determine the correct code.

1b. Define even and odd parity. With the help of the generalized form of the Hamming code, explain how the number of parity bits required to transmit a given number of data bits.

2a. Discuss about the representation of negative number.

2b. Explain BCD, excess-3 and Gray codes with examples.

3a. Explain exclusive OR (EX-OR) and exclusive-NOR (EX-NOR) logic gates with truth tables.

3b. Explain the complement representation of negative number with examples.

4a. Find the complements of the following:

i) (AB′+C)D′+E

ii) (ABC)′(A+B+C)

iii) AB′C+A′BC+ABC

4b. Generate Hamming code for the given 11-bit message 10101110101 and rewrite the entire message with Hamming code.

5a. i) (BA0.C) 16 = (X)8 ii) (10101100)2 = (X)16 iii) (FFE.C) = (X)2

5b. Perform the following operations using r-1`s complement arithmetic i) (+43)10 – (-53)10 ii) (3F85)16 – (1E73)16.

6a.

(i) Prove the following expression using Boolean algebra and De-Morgan’s theorems.

Y′Z′+W′X′Z′+W′XY+WYZ′=Z′

(ii) Realize f(A,B,C)= AB+ A'B'C using NOR-NOR Realization

6b. Realize all basic logic gates using universal gates.

7a. Solve i) (AD012)16 = (X)5 ii) (5.204)10 = (X)3

7b. State the Boolean algebra postulates and explain in detail with examples.

8a.

(i) What are logic gates? Explain about different logic gates i) OR gate ii) AND gate iii) NAND gate iv) X-OR gate.

(ii) Realize f(A,B,C)= AB+ A'B'C using NAND-NAND Realization

8b.

(i) What are SOP and POS forms of logical functions? Explain the standard or canonical SOP and POS forms.

(ii) Realize xor gate using four NAND gates.

9a. What is an excess-3 BCD code? Which short coming of the 8421 BCD code is overcome in the excess-3 BCD code? Illustrate with the help of an example.

9b. What is duality in switching logic? Explain with examples.

10.

A. Write canonical sum and product for each of the following logic functions,

i)F(x,y)=∑m(1,3)

ii) F = A+B.C

iii) F(x,y,z) = πM(0,6,7)

B. Draw the logic symbol, truth table, and Pin Specifications of:

(i) 7400

(ii) 7402

(iii) 7404

(iv) 7408

(v) 7432

(vi) 7486

Quiz: Unit-1

1) (10001)2 = (_____________)10

2) (0.456)8 = (___________)2

3) A+A'= ______

4) Dual of A.B' is _________

5) The Minimized expression for the function f(A,B,C)= AB'+AB'C is _________

6) Draw the NAND equivalent of NOT gate. ________________

7) g(A,B,C)= AB+BC is SOP/ POS? __________

8) ( (AB'+B'C') . D)' = ______________

9) 2's complement of (-13)10 is _______

10) If Ex-OR gate has A, B as inputs and C as output. Now if A=0, B=1; then C= ___

11) 8-bit signed representation of -15 is ______________

12) A carry was generated in r-1's complement with result 72.345; the answer after correction is __________

13) (1101110)binary = (______________________)Gray

14) Excess-3 code of (0100)2 is __________

15) Value of 9 in 8 4 2 -1 code is ___________

16) Example of Reflective code ____________

17) The condition to obtain number of parity bits based on number of message bits is ______

18) IC 7400 is a _______

19) IC 7402 is a _______

20) IC 7404 is a _______

21) IC 7408 is a _______

22) IC 7432 is a _______

23) IC 7486 is a _______

ANSWERS for UNIT-1:

1) 17

2) 0.100101110

3) 1

4) A+B'

5) AB'

7) SOP

8) (A'+B). (B+C) + D'

9) 2's complement of (-13)10 = 0011

10) 1

11) 10001111

12) carry is added to least significant digit available.

72.345

+ 1

--------------

72.346

---------------

13) (11011100)binary = Gray code = 10110010

14) 0111

15) 1011

16) Gray code, 842-1, 2421, Excess-3 code are examples of Reflective codes

17) 2^p >= m+p+1

18) Dual input Quad NAND

19) Dual input Quad NOR

20) 6 NOT gates IC

21) Dual input Quad AND

22) Dual input Quad OR

23) Dual input Quad Ex-OR

PracticeBits-Unit1 Exam ---- Link

Unit-2

Minimization Techniques, Combinational Logic Design-1

UNIT-2: MINIMIZATION TECHNIQUES: Minimization and realization of switching functions using Boolean theorems, K-Map (up to 6 variables) and tabular method (Quine-McCluskey method) with only four variables and single function.

SOP, POS

SOP = Sum of Products

Ex: AB+ CD

AB is a product term

CD is a product term

Finally Sum of two product terms here, i.e. SOP

POS = Product of Sums

Ex: (A+B).(C+D)

A+B is a Sum

C+D is a Sum

Finally product of two Sums, i.e. POS

f(A,B,C)= Σm (0,4,6,7) is a SOP (Sum of Products)

note: 1. f is a output function representing input literals (or variables) A, B and C.

2. Σ means SOP

3. m means minterms. Here the minterms are 0, 4, 6 and 7

So Σm(0,4,6,7) means SOP with minterms 0,4,6,7.

f(A,B,C)= ΠM (1,2,3,5) is a POS (Product of Sums)

note: 1. f is a output function representing input literals (or variables) A, B and C.

2. Π means SOP

3. M means Maxterms. Here the Maxterms are 1, 2, 3 and 5

So ΠM (1,2,3,5) means POS with Maxterms 1,2,3,5.

Canonical form or Standard Form

Each product term or the sum term must contain all variables for a given function.
Ex1: f(A,B,C)= AB+BC; if we observe the first product term AB it does not contain the variable C; Similarly the term BC doesnot contain variable A.
Ex2: g(x,y,z)= (x+y).(y+z); if we observe the first sum term (x+y) it does not contain the variable z; Similarly the term (y+z) doesnot contain variable x.

SOP rule: (A.1 =A)
multiply AB with 1;
Beause the missing variable is C;
1= C+C' ;
So, AB.1 = AB.(C+C') = ABC+ABC'

POS rule: (A+0 =A)
add (x+y) with 0;
Beause the missing variable is z;
0= z.z' ;
So, (x+y+0) = (x+y+z.z') = (x+y+z).(x+y+z')

Ex3: f(A,B,C)= AB+C; Express f in canonical form
Sol:
AB+C =
AB.1 + C.1.1
= AB (C+C') + C.(A+A').(B+B')
= ABC+ABC'+ (AC+A'C).(B+B')
= ABC+ABC'+ [ABC+AB'C+A'BC+A'B'C]
= ABC+ABC'+ [ABC+AB'C+A'BC+A'B'C]
{since A+A=A, ABC+ABC= ABC}
= ABC+ A'BC+AB'C+ABC'+A'B'C

Ex4: f(A,B,C) = (A+B).C; Express f is canonical form.
Sol:
(A+B).C
= (A+B+0).(C+0+0)
= (A+B+CC').(C+AA'+BB')
= (A+B+CC').(C+AA'+BB')
= (A+B+C)(A+B+C') (C+A+B) (C+A+B') (C+A'+B)(C+A'+B')
removing duplicate terms
= (A+B+C).(A+B+C').(A+B'+C).(A'+B+C).(A'+B'+C)

Minimization techniques using:
(i) Boolean Theorems
(ii) K_Map
(iii) Quine Mc Cluskey method(Tabular method)

(i) Boolean Theorems
Example: Minimize the expression AB+AB'+ ABC +A'BC using Boolean Theorems
Sol:
Method_1 =AB+AB'+ ABC +A'BC
=A(B+B')+ BC(A+A') B+B'=1
=A+BC

Method_2 =AB+AB'+ ABC +A'BC
=A(B+B'+BC)+ A'BC
=A+A'BC
=A+BC (by Redundant law, A+A'B= A+B)

(ii) K-Map

K-Map is in the name of the scientist " Karnaugh". The method is Karnaugh-Map method (in short called as K-Map).
K-Map method is convenient upto SIX variables. Easy with 2, 3, 4 variables.

For example, if there are TWO variables, then they can generate AB=00, AB=01, AB=11, AB=10 as four combinations. Remember to write the binary as 1-bit change. Here it is 0,1 on both sides. So not an issue.

2-variable K-Map

3-variable K-Map

4-variable K-Map

5-variable K-Map

6-variable K-Map

(iii) Quine Mc Cluskey method(Tabular method)

Example: Minimize the following function using the Quine-McCluskey method. Y(A, B, C, D) = ∑m (0, 1, 2, 3, 5, 8, 9, 10, 11, 13, 14).

(Scheme: Split of min terms based on number of 1’s (column-1)= 1M; Column-2 = 1M; Prime Implicant chart= 1M; EPI=1M; SOP =1M)

Sol:

STEP1: Write binary values of given min-terms

STEP2:

Table-1 to obtain Prime Implicants.

column-1:Group the min terms in the order of no. of 1's in their binary equivalent.

Coumn-2: Then observe 1-bit change between each group, with term by term comparison. If a bit change occurs ,replace it with '-'.

Column-3: Do the same process as done with column-2 here also. To do easy, observe a '-' in the same location in the other group. Then only compare for 1-bit change. If a bit change occurs ,replace with '-'.

If possible, extend the column-3 process to column-4. If not, it can be done manually also.

STEP3:

Essential Prime Implicant Chart:

Essential Prime Implicants are those, that cover most of the min-terms. Put a tick-mark on top of the min-terms covered by the prime-implicants obtained in previous step. Here B' is a must, as it covers most of the min-terms. Hence it is an Essential Prime Implicant.

The left over min-terms are 5, 13, 14. Check for any possibilities in any column, covering these min-terms. 5,13 are covered by C'D (in column-3, --01). Now the left over min-term is 14. Check for its coverage in column-2 or else last option is column-1. In cloumn-2, min-term-14 is covered by (10,14 = 1-10 = ACD').

So the minimized expression for given function is Y= B' + C'D+ ACD'

Half Adder

* it has 2-inputs; A, B;
* two outputs; S, Co; (S= Sum, Co = Carry out)
*Logic Block

* Truth Table:

* From the above table: Sum = S= AB'+A'B = A XOR B = A ⊕ B; It requires two-input Ex-OR gate
* Carry out = Co = AB; It requires two-input AND gate
* Logic Diagram:

Full Adder

*Logic Block

* Truth Table:

FA METHOD-1 (using Boolean Theorems):
* it has 3-inputs; A, B,Cin
* two outputs; S, Co; (S= Sum, Co = Carry out)
* From the above table: Sum = S = A XOR B XOR Cin= A ⊕ B ⊕ Cin; It requires three-input Ex-OR gate OTHERWISE two 2-input xor gates cascaded
* Carry out = Co =A'BC+ AB'C+ABC'+ABC
(now take common AB from last two terms)
{Also take common Cin, from first two terms}
= A'BCin+ AB'Cin+ABCin'+ABCin
= Cin {AB'+A'B} + AB( Cin+Cin')
= Cin {A ⊕ B} + AB
rearrange the terms
Co = A.B + (A ⊕ B).Cin;
* Logic Diagram:

FA METHOD-2 (using k-maps):
* it has 3-inputs; A, B,Cin
* K-Maps for Sum, Carryout:

* From the above K-Maps: Sum = S = A XOR B XOR Cin= A ⊕ B ⊕ Cin; It requires three-input Ex-OR gate OTHERWISE two 2-input xor gates cascaded
* Carry out = Co = A.B + B.Cin + A.Cin
* Logic Diagram:

FA METHOD-3 (using TWO-Half Adders):
* Requires two HAs, AND gate
* From the above table: Sum = S = A XOR B XOR Cin = A ⊕ B ⊕ Cin; It requires three-input Ex-OR gate OTHERWISE two 2-input xor gates cascaded
* HA1: S= A ⊕ B;
Co = AB
* HA2: Input1 =S= A ⊕ B; input2= Cin; Output1= Sum= A ⊕ B ⊕ Cin
Output2 = (A ⊕ B).Cin; But Co = A.B + (A ⊕ B).Cin; This requires an OR Gate with inputs output2 and Co of HA1;
* So, Carry out = Co = A.B + (A ⊕ B).Cin;
* Logic Diagram:

Half Subtractor

Inputs= A,B
Outputs= Bo, D

Truth Table:

Bo = A'.B
D = A.B'+A'.B = A ⊕ B

Full Subtractor

Inputs= A, B, C;
Outputs = Bo, D;

Truth Table:

Method-1: (using Boolean Algebra)
Bo = A'.B'.C + A'.B.C' + A' .B .C + A. B. C
--> Bo = A'.B'.C + A'.B.C' + A' .B .C + A. B. C
--> Bo = A'.B (C + C') + C. (A'B' +AB)
--> Bo = A'.B + C. (A⊕B)'
D= A'B'C+A'BC'+AB'C'+ABC
--> D = A ⊕ B ⊕ C

Method-2: ( FS using two HS)
here using Boolean Algebra again, we express FS in terms of two HS. Bo = A'.B'.C + A'.B.C' + A' .B .C + A. B. C
--> Bo = A'.B'.C + A'.B.C' + A' .B .C + A. B. C
--> Bo = A'.B (C + C') + C. (A'B' +AB)
--> Bo = A'.B + C. (A⊕B)'
D= A'B'C+A'BC'+AB'C'+ABC
--> D = A ⊕ B ⊕ C
i.e.,
HS1: inputs= A,B; Outputs = Bo1, D1
Bo1 = A'. B
D1= A ⊕ B
HS2: inputs= A ⊕ B, C; Outputs = Bo, D
Bo = (A ⊕ B)'. C + A'B A'B term requires an OR gate
D= (A ⊕ B) ⊕ C

Method-3: ( using K-Maps)
Kmap for Bo:

Kmap for D:

D = A ⊕ B ⊕ C
Bo = (A ⊕ B)'. C + A'B

4bit Binary Parallel Adder(Ripple Carry Adder)

4 bit Binary Subtractor

Adder/Subtractor

BCD Adder using 4bit Binary Parallel Adder

PASTE HERE MATTER

Excess-3 Adder using 4bit Binary Parallel Adder

PASTE HERE MATTER

Code Converters using K-Map

PASTE HERE MATTER

Assignment-2

Assignment-2

UNIT-2:

1a. Design 1-bit full adder using two half adders. Draw the logic diagram with its truth table.
1b. Design a 4-bit carry ahead adder circuit.
2a. Draw the circuit diagram of a 4-bit adder-subtractor and briefly describe its functional principles.
2b. Draw the logic diagram of a three digit Excess-3 adder? And briefly describe its functional principle.
3a. Explain about three and four variable K-map.
3b. Explain in detail about five and six variable K-map.
4a. Explain the operation of carry look-a-head adder.
4b. Implement the NOR gate realization of full adder.
5a. Minimize the following function using the Quine-McCluskey method. Y=∑(1,2,5,8,9,10,12,13,16,18,24,25,26,28,29,31).
5b. Simplify the following Boolean expression to a minimum number of literals,
i) X′Y′+XY+X′Y
ii) (X+Y) (X+Y′)
iii) X′+XY+XZ′+XY′Z′
6a. Simplify the following to least number of literals by manipulation of Boolean algebra.
i) AB′C′D+A′B′D+BCD′+A′B+BC′
ii) ABC+A′B+ABC′
iii) X+XYZ+X′YZ+XW+XW′+X′Y
6b. Simplify the function using six variable K-map F(A,B,C,D,E,F)=∑m(0,5,7,8,9,12,13,23,24,25,28,29,37,55,56,57,60,61).
7a. Write a short note on Full Adder.
7b. Write a short note on Half subtractor.
8a. Design and explain BCD to decimal decoder and draw its logic diagram.

Unit-2 Quiz

UNIT-2:

1. Techniques for Minimization of SOP/ POS are ____________, ____________, ___________.

2. Quine-McCluskey method is also called as -_________________

3. Minimized expression for function f(A,B,C)=Σm (0,1,2,3,4,5,6,7)= _______

4. First step involved in Tabular method is ______________

5. To minimize a 6-variable function, how many k-maps are required? ______

6. How many adjacent 1's can be grouped in k-map? ________

7. A+A'B= _______

8. f(A,B,C)=Σm (0,1,2,3,4,5,6,7). In the expression: 0,1,.. are called as ________

9. f(A,B,C)=πm (0,1,2,3,4,5,6,7). In the expression: 0,1,.... are called as _______

10. Don't care is used even if it is not necessary. True/False

11. Which is slower Serial Adder or Parallel Adder? _________

12. Parallel adder is also called ___________

13. Gate used make an Adder IC into an Adder or Subtractor logic is _______

14. If mode (m) is '1' in adder/ subtractor IC, then it works as _______

15. To avoid delay from each FA of a Parallel adder, instead which adder is used? ___________

16. The Minimized expression for given k-map is _________

17. Minimized expression for given function is ___________

18. Minimized expression for given function is _________

19. Minimized expression for given function is __________

20. Minimized expression for the given function is ____________

21. Minimized expression for the given function is ___________

22. Minimized expression for the given function is ___________

Unit-2 Bits Key:

1. Boolean Theorems, K-Map, Quine-McCluskey method (Tabular method)

2. Tabular Method

3. f=1

4. Arrange minterms in the increasing order of number of 1's in binary equivalent (in groups)

5. Four

6. 2 power i.e. 1, 2, 4, 8, 16, ....

7. A+B

8. minterms

9. Maxterms

10. False

11. Parallel Adder

12. Ripple Carry Adder

13. Ex-OR

14. Subtractor

15. carry look ahead adder

16. f= B'D'

17. f= D'

18. f= 1

19. f= BD

20. (A+B'+D'). (A'+B+D')

21. f=0

22. f=(A+B).(C'+D).(B+C')

PracticeBits-Unit2 Exam ----Link

Decoder

PASTE HERE MATTER

Encoder

PASTE HERE MATTER

Multiplexer (Mux)

PASTE HERE MATTER

Demultiplexer (Demux)

PASTE HERE MATTER

Priority Encoder

PASTE HERE MATTER

7-segment Decoder, display

PASTE HERE MATTER

Implementation of combinational logic using: (b)Mux (b)Decoder

PASTE HERE MATTER

Assignment-3_1

Assignment-3a

UNIT-3_Part-1:

1a. What is encoder? Design octal to binary encoder.
1b. Briefly describe about the priority encoder with suitable diagram.
2a. Implement the following Boolean function with a multiplexer, i) F(A,B,C,D) =∑(1,2,5,8,6,10,12,14) ii) F(A,B,C,D) =∑(1,2,5,6,12).
2b. What is decoder? Construct 3*8 decoder using logic gates and truth table.
3a. Design 8*1 multiplexer using 2*1 multiplexer.
3b. Use a 3x8 decoder to produce, square of a given 3bit number.
4a. Design full adder from 3 to 8 decoder..
4b. Differentiate Demultiplexer and Decoder.
5a. Define multiplexer and explain the procedure to implement 32*1 MUX by using 4*1 multiplexers.
5b. Explain briefly about seven segment displays.
6a. Design a 1:8 demultiplexer using two 1:4 demultiplexer.
6b. Implement a 64:1 MUX using 16:1 and 4:1 MUXs.
7a. Implement f(A,B,C,D) = ∑(0,1,3,5,6,8,9,11,12,13) using 8:1 MUX and explain its procedure.

Quiz: Unit-3_1

UNIT-3 (for Mid-1 only)

For the questions 1 to 5, specify the inputs x outputs

1. Decoder has _______________ specify the inputs x outputs

2. Encoder has _______________ specify the inputs x outputs

3. Multiplexer has _____________________, ___________ selection lines.

4. Demultiplexer has ___________________, ___________ selection lines.

5. Priority encoder has ________________ specify the inputs x outputs

6. In a 4x2 priority encoder, if input ABCD = 0110 (with A=MSB, D=LSB) then output is (with P=MSB, Q= LSB) PQ = ________

7. The minimized expression for the below k-map is:

8. 4x1 Mux has ___________number of selection lines

9. Demux can also be used as a ________________

10. Mux is called as ________________

11. Demux is called as _________________

12. if a 2x1 mux has all inputs connected to logic '1', then output is ___________

13. if a 4x1 mux has inputs i0,i1, i2, i3 = 1,0,0,0 and selection lines s1,s0= 1,0; then output is _____ assume s1 as LSB

14. logic gate required to implement 4x16 decoder using two 3x8 decoders is ________

15. IC 7442 is a _________

16. IC 7447 is a _________

17. IC 7485 is a _________

18. IC 74154 is a _________

Answers for Unit-3 (Mid-1 only):

1. n x 2^n

2. 2^n x n

3. 2^n x 1 , n=selection lines

4. 1 x 2^n , n=selection lines

5. 2^n x n

6. PQ =10

7. A+ B'D'

8. 2

9. Decoder

10. Data selector

11. Data Distributor

12. 1

13. 0

14. NOT gate

15. BCD to decimal decoder

16. BCD to 7 segment display decoder

17. 4-bit digital comparator

18. 4x16 decoder/ demux

PracticeBits-Unit3_1 Exam ----Link

PROM

PASTE HERE MATTER

PAL

PASTE HERE MATTER

PLA

PASTE HERE MATTER

Assignment-3b

Assignment-3b

UNIT-3-Part2:

1a. Write the comparisons between ROM and PLA.
1b. List the merits and demerits of PROM, PAL and PLA.
2a. Use a PROM to produce, square of a given 3bit number..
2b. Implement f(A,B,C)= ∑m(0,1,2,4) and g(A,B,C)= ∑m(0,5,6,7) using PROM.
3a. Implement f(A,B,C)= ∑m(0,1,2,4) and g(A,B,C)= ∑m(0,5,6,7) using PLA.
3b. Implement f(A,B,C)= ∑m(0,1,2,4) and g(A,B,C)= ∑m(0,5,6,7) using 4-wide logic PAL.
4a. Implement a Full adder using PLA.
4b. Use a PROM to generate a Gray code from 4-bit Binary number.

Quiz: Unit-3b

Unit-3_2 Quiz

UNIT-3 (for Mid-2 only)

1. PROM has __________ Programmable logic, ________ fixed logic.
2. PAL has __________ Programmable logic, ________ fixed logic.
3. PLA has __________ Programmable logic, ________ fixed logic.
4. For given functions f(a,b,c) and g(a,b,c); which programmbale device has programming table has last columns as f(T), g(F) implementations? ______
5. PAL abbreviation: _____ _____ _____
6. If you are asked to Design a FullAdder using PROM, size of PROM required is __x__
7. 3-input, 4 wide logic PAL means: ______, ______, _____
8. Example of PLD: _______
9. PLDs are preferred because _______
10. Number of inputs in a 128x3 PROM is/are ______

KEY for bits Unit3_2:
1. OR, AND
2. AND, OR
3. AND and also OR, -
4. PLA
5. Programmable Array Logic
6. PROM contains a Decoder followed by programmable outputs
Here FA--> i/p=3 (A,B,Cin); o/p=2 (Sum, Cout);
inputs are 3; so decoder is 3x8;So PROM input size= 8;
outputs are 2; so PROM outputs=2;
So PROM size is 8x2;
7. PAL accepts 3-variables as input.
first four AND gate outputs are connected to an OR gate
similarly the next four AND gate are connected to another OR gate
8. PLA you may also write PAL or PROM 9. it is Easy to modify and implement a design
10. 7
2 power 7 is 128

PracticeBits-Unit3_2 Exam ----Link

Sequential Logic

Sequential Logic_Syllabus

UNIT-4:

SEQUENTIAL CIRCUITS-I: Classification of sequential circuits (synchronous and asynchronous), operation of NAND & NOR latches and flip-flops; truth tables and excitation tables of RS flip-flop, JK flip-flop, T flip-flop, D flip-flop with reset and clear terminals. Conversion from one flip-flop to another flip- flop. Design of ripplecounters, design of synchronous counters,Johnson counter, ring counter. Design of registers- Buffer register,control buffer register,shift register, bi-directional shift register, universalshift, register. Study the following relevantICs and their relevant functions 7474,7475,7476,7490,7493,74121.

UNIT-5:

SEQUENTIAL CIRCUITS II: Finite state machine; state diagrams, state tables, reduction of state tables. Analysis of clocked sequential circuits Mealy to Moore conversion and vice-versa. Realization of sequence generator, Design of ClockedSequential Circuit to detect the given sequence (with overlapping or without overlapping).

PART2

Introduction

Comparison of Combinational logic with sequential logic

Combinational logic

sequential logic

1. No feedback used OR Memory element not used.

2. Can not be used to store output.

3. Operates faster (only gate delays are accountable)

1. Feedback forms either Synchronous Sequential logic and Asynchronous sequential logic. FlipFlop is basic memory element

2. FF stores 1-bit data. (either 0 or 1)

3. Operates slower compared to Combinational logic

Sequential logic is classified as:

Synchronous Sequential logic

Asynchronous sequential logic

1. CLK used

2. Operates slower, as it depends on CLK

3. Easy to design

1. CLK not used

2. Operates faster, as it does not depend on CLK

3. Complex design

Basic element of sequential circuits, is FlipFlop (FF) which is a 1-bit storage block.(so a Flip-flop stores either 1 or 0). A series of FF may work as either Registers or Counters.

To study FF, we need to study basic part of a FF i.e., Latch

2. Latches FlipFlops

Latch SR FF

a. SR Latch JK FF

b. S’R’ Latch D FF

Gated Latch T FF

a. Gated SR Latch

b. Gated D Latch

FF triggering types:

Latch

Flipflop

1. Asynchronous sequential circuit

2. CLK not used

3. Operates faster, as it does not depend on CLK

1. Synchronous sequential circuit

2. CLK used

3. Operates slower, as it depends on CLK

PART3

Latches

Video showing Latch working :

Latch may be using either NOR or NAND gates.

RS Latch or SR Latch: (it uses NOR gates.)

Truth table of RS latch: (i,e., using NOR gates)

S R Q Qn+1 state

0 0 0 0 NC

0 0 1 1 NC

0 1 0 0 Reset

0 1 1 0 Reset

1 0 0 1 Set

1 0 1 1 Set

1 1 0 x Invalid

1 1 1 x Invalid

The state is called Invalid state as Qn+1=0, Qn+1'=0 both are not complementary to each other.

S’R’ Latch: (it uses NAND gates:)

Truth table of S'R' latch: (i.e., using NAND gates)

S R Q Qn+1 state

0 0 0 x Invalid

0 0 1 x Invalid

0 1 0 0 Set

0 1 1 0 Set

1 0 0 1 Reset

1 0 1 1 Reset

1 1 0 0 NC

1 1 1 1 NC

The state is called Invalid state as Qn+1=1, Qn+1'=1 both are not complementary to each other.

PART4

Gated Latches

Gated Latches: (Logic symbol, Logic diagram, Truth table)

Gated SR Latch:

EN S R Q Qn+1 state

1 0 0 0 0 NC

1 0 0 1 1 NC

1 0 1 0 0 Reset

1 0 1 1 0 Reset

1 1 0 0 1 Set

1 1 0 1 1 Set

1 1 1 0 x Invalid

1 1 1 1 x Invalid

0 x x 0 0 NC

0 x x 1 1 NC

Gated D Latch:

EN D Q Qn+1 state

1 0 0 0 Reset

1 0 1 0 Reset

1 1 0 1 Set

1 1 1 1 Set

0 x 0 0 NC

0 x 1 1 NC

PART5

FlipFlops

FlipFlops: (Logic Symbol, Logic diagram, Truth table, Characteristic equation)

Level triggered FF are outdated models (to understand its issues, we study it in SR FF and JK FF). Only Edge triggered are used for best performance.

SR FF:

Level triggered SR FF:

Edge Triggered SR FF:

JK FF:

In level triggered FF, let delay of each gate is Δt and pulse width (CLK) be Tp.

if Tp > Δt, Race around occurs if J=K=1. It means output continuously Toggles from 0 to 1 and 1 to 0, and so on.
So, to avoid race around condition, it is necessary to choose Tp < Δt. If J=K=1, in such case output toggles once and stops there (from toggling again).

In edge triggering, there is no race around condition, as (rising/ falling) edge lasts for a few fraction of time, which is very small comparative to gate delay Δt. Here also output toggles once and stops there (from toggling again).

D FF:

NOTE: D FF can be implemented using SR FF also.

T FF:

PART6

FF Excitation Tables

Excitation Table for SR FF

Excitation Table for JK FF

Excitation Table for D FF

Excitation Table for T FF

PART7

FF Conversions

Ex1: Convert SR FF to D FF

Sol:

STEP1: Write Truth Table for D FF

STEP2: Now use Qn, Qn+1 to write excitation table for SR FF

STEP3: Now Draw K-Map for

D,Qn for S
D,Qn for R

STEP4: Realize the converted FF.

S= D, R= D' are the conversion equations.

-----------------------------------------

Try these:

Ex2: Convert JK to SR FF

Ans: J=S, K=R

Ex3: Convert D FF to T FF

Ans: D= T ' Qn + T Qn '

-----------------------------------------

-----------------------------------------

Ex4: Convert T FF to SR FF

Sol:

FF conversion table

T= S' R Qn + S R' Qn '

PART8

Asynchronous Counters

Aslo called Ripple counters. Only first FF (it's o/p is the Lsb)

Classified as:

1. Up

2. Down

3. Up/Down

Asynchronous Counters (Ripple Counters):

Down counter: (++, --)

Up counter: (+-, -+)

OR

Ex5: Design a ripple 2bit up counter

Sol: 2-bits= 2 FF = 4 states i.e.

And the cycle repeats.

Below is the state diagram:

Logic Diagram for ripple 2bit up counter:

Ex6: Design a ripple 2bit down counter

Sol: 2-bits= 2 FF = 4 states i.e.

And the cycle repeats.

Below is the state diagram:

Logic Diagram:

-----------------------------------------

Try this:

Ex7: Solve , 3bit ripple down counter.

-----------------------------------------

Ex8:Design a Mod-5 ripple up counter

Sol:

Mod= Modulo;

Mod-5 means, it has 5 states.

No of states=5 à(counts from 0 to 4

ð 000, 001, 010, 011, 100 these are to be counted. (Left over states means, the states that are not to be counted are 101, 110 and 111)

ð So, No. of FF =3 (as 3 bits are required to count five states)

The counter must reset when it reaches 101 (invalid state). In this situation, Q₂ =1, Q₁=0, Q₀ =1

So, if Q₂Q₀ =1 then Counter must reset. For CLR’ 0 is required, so AND must be followed by NOT gate. Hence a NAND gate is used.

K-Map for RESET

Logic diagram for Mod-5 ripple up counter

NOTE: Above diagram is same as below: (If J=K=1, its T-FF)

Ex9:Design a Mod-5 ripple down counter

Sol:

No of states=5 à(counts from 7 to 3)

ð 111, 110, 101, 100, 011 these are to be counted. (Left over states means, the states that are not to be counted are 010, 001, 000)

ð So, No. of FF =3 (as 3 bits are required to count 5 states)

The counter must reset when it reaches 010 (invalid state).

-----------------------------------------

Try these:

Ex10: Design a Mod-10 ripple up counter.

Hint: 10 states i.e., from 0 to 9; so 0000 to 1001. At 1010, counter must reset.

Ex11: Design a Mod-10 ripple down counter.

Hint:10 states i.e., from 15 to 6; so 1111 to 0110. At 0101, counter must reset.

PART10

Synchronous Counters

CLK is common to all the FFs. So, There is no difference in using all +ve edge FF OR using all -ve edge FFs

Ex12: 2-bit Synchronous up counter.

Sol:

since it is 2bit, the counter requires TWO flipflops.

STEP1. Write PS, NS as per the counter working.

STEP2. J1 K1 are the Excitation values of PS(Q1) and NS(Q1); Similarly J0 K0;

PS NS J1 K1 J0 K0

Q1 Q0 Q1 Q0

0 0 0 1 0 x 1 x

0 1 1 0 1 x x 1

1 0 1 1 x 0 1 x

1 1 0 0 x 1 x 1

STEP3.

Obtain equations for J1, K1, J0, K0; for example (J1 and PS).

PS NS J1 K1 J0 K0

Q1 Q0 Q1 Q0

0 0 0 1 0 x 1 x

0 1 1 0 1 x x 1

1 0 1 1 x 0 1 x

1 1 0 0 x 1 x 1

Similarly K-Maps for (K1 and PS), (J0 and PS), (K0 and PS).

k-maps for other inputs

STEP4:

Realize Logic Diagram

Logic diagram for 2-bit synchronous up counter

STEP5:

State diagram

Try these:

Ex13: 3bit synchronous synchronous down counter using D-FF.

Ex14: Design a Mod-10 synchronous up counter using T-FF.

PART11

Registers

1. FF can store a single bit, either '0' or '1';

2. To store or retrieve multiple bits, a Register is used.

3. Buffer Register (It is a basic configuration of Registers)

4. Types of Registers

Classification based on Serial / Parallel OR input/output:

Parallel in Parallel out (PIPO)
Parallel in Serial out (PISO)
Serial in Parallel out (SIPO)
Serial in Serial out (PIPO)

Classification based on Shifting property:

Left Shift Register_SISO
Right Shift Register_SISO

4-Bit Buffer Register:

D0, D1, D2, D3 load data parallelly, and at Q0,Q1,Q2,Q3 data retrieved parallelly.

PIPO Register:

D0, D1, D2, D3 load data parallelly, and at Q0,Q1,Q2,Q3 data retrieved parallelly.

SIPO Register:

data loaded at D0 serially, and at Q0,Q1,Q2,Q3 data retrieved parallelly.

SISO Register:

data loaded at D0 serially, and at Q3 data retrieved serially.

PISO Register:

NOTE: Shift = Load'

Data loaded at B01,B1, B2, B3 parallelly, and at Q3 data retrieved serially.

Shift=1:

input to AND gate are Q0 and Shift=1; (other AND gate has Load' =0, output is 0). While Shift operation:

if Q0= 0, Shift=1, then AND gate o/p =0. So Q0=0 is input to D1
if Q0= 1, Shift=1, then AND gate o/p =1. So Q0=1 is input to D1

Shift=0:

input to AND gate are Q0 and Shift=0; So o/p= 0 for first AND gate. While Shift operation:

if Q0= 0, Shift=1, then AND gate o/p =0. So Q0=0 is input to D1
if Q0= 1, Shift=1, then AND gate o/p =1. So Q0=1 is input to D1

PART12

Special Counters

1. Ring counter:

State Table

Q₀ Q₁ Q₂ Q₃

1 0 0 0

0 1 0 0

0 0 1 0

0 0 0 1

State diagram of Ring counter

Ring counter Logic diagram

2. Twisted Ring counter OR Johnson's Counter:

State Table

Q₀ Q₁ Q₂ Q₃

0 0 0 0

1 0 0 0

1 1 0 0

1 1 1 0

1 1 1 1

0 1 1 1

0 0 1 1

0 0 0 1

0 0 0 0

State diagram of Twisted Ring counter

Logic diagram of Twisted Ring counter

Ex15: Design a 2-bit ripple up/down counter.

Sol:

Decide initially: Using a -ve edge triggered T-FF.

use Ex-OR gate to create a mode.

Let M= mode = an input to ExOR gate

Qo = output (LSB) = another input to ExOR gate.

if M=0, o/p of ExOR gate is Qo

if M=1, o/p of ExOR gate is Qo '

so if M=1, then its - - logic, a Down counter

if M=0, then its + - logic, an Up Counter.

logic diagram for 2-bit Ripple Up/Down counter

state diagram for 2-bit up/down counter

---------------------------------

Try these:

Ex16: Design a 3-bit ripple up/down counter using -ve edge triggered T-FF.

Hint: requires two ExOR gates i.e., from Q0, another from Q1;

Ex17: Design a Mod-10 ripple up/down counter using +ve edge triggered JK FF.

----------------------------------

* Ex18: Design a synchronous 4-bit up/down counter.

* is mentioned for this model, as the procedure used in this design is used in designing Mealy m/c and Moore m/c also.

Sol:

state diagram for 2-bit up/down counter

Assumptions/ Definitions:

1. Let

M=0 is a up counter
M=1 means Down counter

2. the design is being done using D-FF.

STEP1:

Obtain the state table
here design to be done using D-FF; Hence the excitations for 2-bits Q1Q0 are D1D0.

STEP2:

Obtain D1 and D0 equations using k-map (PS,M)

for D1 (wherever 1 or X is present, to be plotted in k-map): PS,M = Q1,Q0,M
for D0 (wherever 1 or X is present, to be plotted in k-map): PS,M = Q1,Q0,M

similarly draw k-map for D0:

STEP3:

realize the counter based on the equations obtained.

Ex19: Compare Synchronous and Asynchronous counters.

Sol:

Ex20: Show that Ripple counter can be used as a frequency divider. OR

Explain the significance of cascading the ripple counters.

Sol:

Using Mod-M counter cascading with Mod-N counter gives Mod-MN counter. for example, Mod-10 + Mod-6 = Mod-60 counter

considering another example,

cascading Mod-counters

Mod-5 and Mod-4 are cascaded. So final counter is a Mod-20 counter.

Mod-20 counter implementation using Mod-5 and Mod-4 counters

Note: In order to cascade:

1. All FF must be with same Trigger

2. Counters cascaded must be either UP / Down counter (can't mix an up with down counter)

-----------------------------------
Try these:

Ex21: Design a Mod-16 ripple up counter by employing Mod-2, Mod-4, Mod-2 counters. Use -ve edge triggered T-FFs.

------------------------------------

Ex22: If the CLK frequency is 8.192 MHz, what is the frequency of msb for a binary ripple counter required to count (16383)₁₀

If the CLK frequency is 8.192 MHz, what is the frequency of msb for a binary ripple counter required to count (16383)₁₀

Sol:

from given data N=16383, f= 8.192MHz

Generally to count N states for a Mod-N counter, requires n FFs.

with n FFs, max number of states that can be counted are 2ⁿ- 1

i.e. N ≤ 2ⁿ- 1

16383 = 2ⁿ- 1

2ⁿ= 16384

taking log₂ on both sides, log₂ (2ⁿ) = log₂ (16384)

n = log₂ (2¹⁴)

n= 14 (---> there are 14 FFs)

Now frequency of any bit position (x bit) is

f_x = f/ 2^x

Here to calculate for msb, i.e., 14th bit.

f_14 = 8.192MHz / 2¹⁴

--> f_14 = 500 Hz

------------------------------------

Assignment-4

Assignment-4

UNIT-4:

1a. Explain about types of sequential circuits.
1b. Conversion of SR flip-flop to T-flip-flop.
2a. Draw and explain the logic diagram for a 4-bit binary ripple down counter using positive edge triggered flip-flops.
2b. Explain the Buffer Register and Control Buffer Register.
3a. What do you mean by triggering? Explain the various triggering modes with examples.
3b. Convert T flip-flop to D flip-flop.
4a. Design a modulo-12 up synchronous counter using T-flip flops and draw the circuit diagram.
4b. Explain in detail about shift registers.
5a. Explain the operation of D-flip flop with the help of truth table.
5b. Explain the basic principles of ripple counter.
6a. Design a Mod-6 synchronous counter using J-K flip flops.
6b. Draw and explain the working of shift right register.
7a. Explain about master-slave flip-flop in detail.
7b. Design a 4-bit ripple counter using T-flip-flop. Explain using waveforms.
8a. Design and explain a 4-bit ring counter using D-flip flops with relevant timing diagrams.
8b. Draw a 4-bit bi-directional shift register logic diagram and explain its operation.

Quiz: Unit-4

Quiz:Unit-4

UNIT-4

1. Latch is a _______ without _______
2. FlipFlop is a _______ with _______
3. Characteristic Equation of SR FF: Qn+1 = _________
4. Characteristic Equation of D FF: Qn+1 = _________
5. Characteristic Equation of T FF: Qn+1 = _________
6. Characteristic Equation of JK FF: Qn+1 = _________
7. If Qn=0, Qn+1 = 1 for a T-FF, then T= _______
8. In a JK-FF, if J=0, K=1, Qn=1 then Qn+1 = _______
9. In a JK-FF if J=1,K=1 and when clock goes high for a longer duration (greater than delay of gates), this condition is called _______
10. Mod-N counter has ____ number of states.
11. A 4-bit register stores ____ number of bits.
12. Johnson's counter is also called as __________ ________.
13. No. of states in ring counter= _____ .
14. No. of states in a Johnson's counter = ___.
15. Universal Shfit Register has combinational element _____ and sequential element ____ combinedly to produce Left/Right shift, Load operations.
16. If CLK' and Q' are coupled to each other in case of T-FF, it is a ________ _______ counter.

Unit-4 bits Key
1. single bit memory device, clock
2. single bit memory device, clock
3. S+R'Q
4. D
5. TQ' +QT'
6. JQ' +K'Q
7. 1
8. 0
9. Race around condition
10. N
11. 4
12. Twisted Ring
13. 4
14. 8
15. Mux, D-FF
16. Ripple Down (Asynchronous Down)

PracticeBits-Unit4 Exam ----Link

PART13

State Table

Sequential Logic Design_Part2:

Before learning sequence detectors, things to be learnt are:

1. State table from state diagram (or Vice-versa)

2. State table reduction

3. Mealy Machine and Moore Machine

1. State diagram from State Table:

Ex23: Obtain the state diagram from state table.

Sol:

STEP1:

Draw all the states with neat spacing.

STEP2:

we write x_value / output i.e., generally x/y on the line drawn from a to b

STEP3:

STEP4:

STEP5:

STEP6:

similarly after drawing all the states and

Ex24: Obtain the state diagram from the state table given.

Sol:

STEP1:

Draw all states spacially

STEP2:

Write outputs of all PS

final figure is below with all outputs indicated:

STEP3:

STEP4:

STEP5: Similarly complete all the states and state values

state diagram of given Moore Machine

Ex25: Obtain the State table from the state diagram

Sol:

By observing the given figure:

the states are a,b,c,d
Its a Moore machine (output does not depend on input)

STEP1: Draw a Table with PS, NS (x=0, x=1), output=y

STEP2:

observing the outputs:

for state a, y=0,

for state b, y=1,

for c, y=0

for d, y=0

STEP3:

fill the next states:

for state a, if x=0, NS=a (itself)

if x=1, NS=b

For state b, if x=0, NS=a

if x=1, NS=d

similarly fill other NS.

-----------------------------------------
Try this:

Ex26: Obtain the State table from the state diagram

-----------------------------------------

2.1 State Table reduction:

Ex27: Reduce the given state Table.

Sol:

STEP1:

Identify same NS and also same O/P

STEP2:

Now remove one of the redundant states. Here either a or c (any one only to be removed)

-----------------------------------------
Try this:

Ex28: Reduce the state table given.

-----------------------------------------

2.2 State Reduction and state assignment:

Ex29: Obtain the characteristic table with proper state assignments for given state table.

Sol:

STEP1: reduce redundant states

STEP2:

STEP3:

replace all duplicate states with the alternate state variable

STEP4:

STEP5:

Now do state assignment;

here a, b, d (three states ==> 3 ==> binary is 11 ==> so two FFs )

Arbitrarily assign values;

a =00 = q2q1

b=01 = q2q1

d=10 = q2q1

STEP6:

Just revise the table with PS,X, NS,Y columns.

STEP7:

Start design using any FF. Let us choose here D-FF for convenience.

STEP8:

Now K-maps for:

PS,x for D2=?
PS,x for D1=?
PS,x for y=?

Note: in the above table 6,7 combinations of q2q1x not present; hence they are don't cares in k-map.

STEP9: K-Maps

STEP10:

Realization of designed Moore Machine

-----------------------------------------
Try this:

Ex30: Realize the following.

PART14

Mealy m/c, Moore m/c and Conversions

3.3a: Conversion of Mealy to Moore:

PS= Present State

NS= Next State

Ex33: Obtain the Moore state table for given machine.

Sol:

STEP1:

Obtain the state table for the given state diagram.

STEP2:

Now observe where the output each PS is varying in the NS

Let o/p = output = y

Now in NS column, check each state has same or different outputs.

if state output does not change, leave that state
if state output changes, split that state into TWO states
ex: while checking for state 'a'; It can be observed that, at a point it has y=0, and also y=1

so a to be split as a0, a1
a0 is state with y=0
a1 is state with y=1

similarly observing for other states also,

for state b: its no change (all its state have output y=1 only). So no need to split b.

for state c: as this state has different outputs, this state is split as c0 (with y=0) and c1 (with y=1)

for state d: no change in y=1; so leave state 'd' as it is.

finally after this process:

a is a0,a1

b is b

c is c0,c1

d is d

writing the outputs for above all states:

a0 --> y=0

a1 --> y= 1

b --> y=1

c0 --> y=0

c1 --> y=1

d --> y=1

The modified table is (Replace the output column y for that of a Moore Machine.):

Mealy m/c TO Moore m/c

i.e. along with outputs

STEP3:

replace the NS properly:

to replace next states of a0:

to replace NS of a1:

to replace NS of b:

to replace NS of c0:

to replace of c1:

to replace of d:

Final Moore Transition table is:

-----------------------------------------
Try this:

Ex34: Convert the Mealy m/c to Moore m/c.

-----------------------------------------

3.3b: Conversion of Moore to Mealy:

PS= Present State

NS= Next State

Ex33: Obtain the Mealy transition table for given machine.

Sol:

STEP1:

Reduce Transition/State table:

identify same NS with same o/p also.
Remove the duplicate PS row.
Replace the duplicate NS values.

STEP2:

split the NS column as NS, o/p for easy procedure.

similarly after NS, place the o/p values :

Mealy m/c converted table

PART15

Analysis of Clocked Sequential Circuits

3.2: Analysis of Clocked Sequential Circuits:

Ex31: Obtain the state table for given machine.

Sol:

STEP1:

By observing the logic diagram,

z= output = y1y2 = q1q2 -----(as output not dependent on input (x), it is Moore Machine)

T1= q2 x

T2 = x

as two FF are used, total output combinations are FOUR i.e., 00,01,10,11 (with both x=0,1)

STEP2:

Prepare a draft state table:

STEP3:

Now start filling the table one by one:

row1:with q2,q1,x = 0,0,0

T2= q2 x = 0 . 0 = 0
T1= x =0
z= q1 q2 =0 . 0 = 0

row2:with q2,q1,x = 0,0,1

T2= q2 x = 0 . 1 = 0
T1= x =1
z= q1 q2 =0 . 0 = 0

STEP4:

Now use the T-FF excitation /Characteristic table:

T-FF Characteristic table

T-FF Excitation table

as a briefing for T-FF, whenever

PS = T, NS=0
PS ≠ T, NS=1

similarly fill all the NS values

STEP5:

Replace 00 with variable 'a'

so 00=a

01=b

10=c

11=d

required is the highlighted part:

Rearrange the x value as

NS at x=0
NS at x=1

Obtain the state diagram for above state table.

-----------------------------------------
Try this:

Ex32: Realize the following.

-----------------------------------------

PART16

Types of Sequence Detectors

Sequence detection is of two types:

Question is: Detect 101 from input sequence:

Sol: Let input sequence is 001110010101101010010.....

Let y= o/p =1 if 101 is detected.

Overlapped Sequence:

Non-overlapped Sequence:

Any mode of sequence detection can be implemented using either Mealy m/c or Moore m/c.

Learn Drawing state diagram for a given sequence detector

Learn to draw state diagram for a given sequence detector

Ex1: Detect 101 from a series of input sequence. Consider without overlapping (Non-overlapping) case.
Sol:
Without overlapping:
Let input sequence x= 1010101100111000101101;
don't forget to take sequence, that must start with sequence to be detected
Step1:

Step2:

Step3:

Step4:

Step5:

Step6:

--------------------------------

Ex2: Detect 101 from a series of input sequence. Consider overlapping case.
Sol:
With overlapping:
Let input sequence x= 1010101100111000101101;
don't forget to take sequence, that must start with sequence to be detected
Step1:

Step2:

Step3:

Step3 (WRONG WAYS):

Step4:

Step5:

Step6:

--------------------------------

Ex3: Draw the state diagram of a non-overlapping 1010 sequence detector.
Sol:

Step1:

Step2:

Step3:

Step4:

Step5:

Problems on Sequence Detectors

Problems on Sequence Detectors

Ex1: Design a non-overlapping 1010 sequence detector.
Sol:

Step1:

Step2:
State table for state diagram

Step3:
State Reduction (if necessary) and State Assignment

Arbitrary state assignment: Let a=00, b=01, c=10, d=11;

Step4:
Modified State Table

Step5:
Excitation values (FF implementation) in Modified Table

Step6:
Equations (using K-Maps) for Excitations and Outputs

Step7:
Realization

--------------------------------

Ex2: Design a non-overlapping 1010 sequence detector using JK-FF.
Sol:

Step1:

Step2:
State table for state diagram

Step3:
State Reduction (if necessary) and State Assignment

Arbitrary state assignment: Let a=00, b=01, c=10, d=11;

Step4:
Modified State Table

Step5:
Excitation values (FF implementation) in Modified Table

Step6:
Equations (using K-Maps) for Excitations and Outputs

Step7:
Realization

Assignment-5

Assignment-5

UNIT-5:

1a. Explain about State diagram and State table in sequential circuits.
1b. Discuss the realization of sequence generator with diagram.
2a. Draw state diagrams of a sequence detector which can detect 110.
2b. Draw and explain Moore circuit.
3a. Explain state transition function, finite state model, Terminal state and strongly connected machine in finite state machine.
3b. Explain the state reduction technique.
4a. Draw state diagrams of a sequence detector which can detect 010.
4b. Draw the diagram of Mealy type FSM for serial adder.
5a. Explain the analysis of clocked sequential circuits.
5b. Implement the Sequential Circuit with clock to detect the given sequence without overlapping.
6a. Draw state diagrams of a sequence detector which can detect 011.
6b. Explain the state machine capabilities and limitations in detail.
7a. Explain the difference among a truth table, a state table, a characteristic table and an excitation table.
7b. Draw state diagrams of a sequence detector which can detect 101.
8a. Explain in detail the Mealy state diagram with one example.
8b. Design the Clocked Sequential Circuit to detect the given sequence with overlapping.

Quiz- Unit-5

Quiz: Unit-5

UNIT-5

1. FSM is a machine that has ______ states.
2. Examples if FSM are ______, _______.
3. Moore machine is independent of input variables. (T/F)
4. Mealy machine depends on input variables. (t/F).
5. If a FSM has output variable equation as given: y= Q2.Q1'.Q0.x ; where Q2,Q1,Q0 are D-FF outputs. x is an input to the machine. Now the machine is ______.
6. If a FSM has output variable equation as given: y= Q2.Q1'.Q0 ; where Q2,Q1,Q0 are D-FF outputs. x is an input to the machine. Now the machine is ______.
7. Number of states ___________ while converting Mealy to Moore machine.
8. Number of states ___________ while converting Moore to Mealy machine.
9. From the figure below: Identify the sequence that is detected by the machine. Also mention whether its overlapping or non-overlapping detector.

10. From the below state table: While converting from Mealy to Moore, Identify whether state-a or state-b is split? If Yes, rename and metion the outputs.

State-a: Split Yes/No. ____
If Yes, New_state= _____
output=____
other_New_state= _____
output=____
State-b: Split Yes/No. ____
If Yes, New_state= _____
output=____
other_New_state= _____
output=____

Unit-5 Bits Key
1. finite
2. Mealy machine, Moore Machine
3. T
4. T
5. Mealy
6. Moore
7. Same or More
8. same
9. 011, Non-overlapping Mealy machine
10. State-a: Split Yes
If Yes, New_state= __a0__,
output=__0__
Other_New_state= __a1__,
output=__1__
State-b: Split No

PracticeBits-Unit5 Exam ----Link

Question Papers, Mid Papers, Key

Question Papers, Key and Scheme

Model Paper-1

"Click on Image to zoom"

Mid-1: Key

Mid-1: Key and Scheme

What is the significance of Hamming code? Determine Hamming code, if message is 1001. Also verify the received hamming code, to recover the message by introducing an error at bit-position-4.

(Scheme: Formula for Hamming code =1M; No of parity bits=1M; Decoding steps=2M; Answer=1M)

Sol:

Hamming code is used to detect single bit error and also correct the same. It can not detect correct more than two errors. Error detection and correction capabilities are achieved by introducing Parity bits in between Message bits at selected locations (at the powers of 2). Generally the Parity followed is EVEN Parity. Even parity means, the number of 1's at the point of comparison are even (i.e., 0,2,4,6,...). If its odd parity, then odd number of 1's (1,3,5,7,9,...).

M= message bits, P= Parity bits

2^P ≥ M+P+1

Here in the problem, M=4 bits;

keep trying until the minimum condition satisfies (true occurs).

M=4, P=1 ⇒ 2^P ≥ M+P+1 ⇒ 2¹≥4+1+1 ⇒ 2≥6 is False

M=4, P=2 ⇒ 2^P ≥ M+P+1 ⇒ 2²≥4+2+1 ⇒ 4≥7 is False

M=4, P=1 ⇒ 2^P ≥ M+P+1 ⇒ 2³≥4+3+1 ⇒ 8≥8 is True. (8=8 Satisfies the condition)

The Hamming code consists of 4-message bits and 3-parity bits; Total=7 bits.

-------------------------------

Minimize the following function using the Quine-McCluskey method. Y(A, B, C, D) = ∑m (0, 1, 2, 3, 5, 8, 9, 10, 11, 13, 14).

(Scheme: Split of min terms based on number of 1’s (column-1)= 1M; Column-2 = 1M; Prime Implicant chart= 1M; EPI=1M; SOP =1M)

Sol:

STEP1: Write binary values of given min-terms

STEP2:

Table-1 to obtain Prime Implicants.

column-1:Group the min terms in the order of no. of 1's in their binary equivalent.

Coumn-2: Then observe 1-bit change between each group, with term by term comparison. If a bit change occurs ,replace it with '-'.

If possible, extend the column-3 process to column-4. If not, it can be done manually also.

STEP3:

Essential Prime Implicant Chart:

So the minimized expression for given function is Y= B' + C'D+ ACD'

-------------------------------

Explain the working of a 8x1 Mux with proper logic diagram and equations. Also Implement f(A,B,C,D) = ∑(0,1,3,5,6,8,9,11,12,13) using 8:1 MUX and explain its procedure.

(Scheme: 8x1 mux symbol=1M; Logic diagram=1M; Problem- Truth table=1M; Obtaining f in terms of D =1M; Problem- Logic diagram=1M)

Sol:

Multiplexer in short called Mux is data selector.

2^n x 1 Mux has n selection lines.

So 8x1 Mux has 3-selection lines. ( 8 x 1 = 2^3 x 1)

Based on the selection line, one of the input is selected and connected to output via logic gates.

If s2s1s0 = 000, Y=D0. Similarly, s2s1s0 = 001, Y=D1. Truth table below explains the combination of s2s1s0 to produce output Y.

Truth table for 8x1 Mux

Logic equation for 8x1 Mux is:

Y= A'B'C' D0 + A'B'C D1 +A'BC' D2 +A'BC D3 +AB'C' D4 +AB'C D5 +ABC' D6 +ABC D7

(note: A'.B'.C.D1 is written in short as A'B'C D1)

logic diagram of 8x1 Mux

logic symbol of 8x1 Mux

STEP1:
ABCD -f
0000-1
0001-1
0010-0
0011-1
0100-0
0101-1
0110-1
0111-0
1000-1
1001-1
1010-0
1011-1
1100-1
1101-1
1110-0
1111-0

STEP2:
Separate ABC (are used as selection lines for 8x1 Mux); relate D and f;

Example:

ABC D -f
000    0-1
000   1-1
_______  f=1;

ABC=000 =D0; Therefore D0= f=1

so fill the table in the above process.

ABC D -f
000    0-1
000   1-1
________f=1
001   0-0
001   1-1
________f=D
010   0-0
010   1-1
________f=D
011   0-1
011   1-0
________f=D’
100   0-1
100   1-1
________f=1
101   0-0
101   1-1
________f=D
110   0-1
110   1-1
________f=1
111 0-0
111 1-0
________f=0

STEP3:
Realize above table using 8x1 Mux

Objective Key

1. Dual of A'+B is _________
(a) AB (b) AB’ (c) A’B (d) A’B’

2. (101110.11)_2 = (_____________)_10
(a) 46.75 (b) 56.25 (c) 46.50 (d) 92.75 (e) 92.50

3. 8-bit signed representation of (-10) is _____________
(a) 00001010 (b) 10001010 (c) 01110101 (d) 11111010

4. Value of 7 in 8 4 2 -1 code is ___________
(a) 0111 (b) 1001 (c) 1000 (d) 1010

5. If Ex-OR gate has A, B as inputs and C as output. When is C=1 for which combination of A,B?
(i) 0, 0 (ii)0, 1 (iii) 1, 0 (iv) 1, 1
(a) (i), (ii) (b) (iii), (iv) (c) (i), (iv) (d) (ii), (iii)

6. Minimized expression for the function f =AB'+AB'C is__
(a) AB’ (b) 1+C (c) A (d) B’

7. ((B'+BC').D)' = ___________ use DeMorgan’s Theorem
(a) (B’. (B'+C’))+D’ (b) (B. (B’+C))+D’
(c) (B. (B+C’))+D’ (d) (B’. (B+C))+D’ (e) NONE

8. If message bits=M, Formula to find number of Parity bits (P) in Hamming code
(a) 2^P ≤ M+P+1 (b) 2^P ≥ M+P+1 (c) 2^M ≥ M+P+1 (d) 2^M ≤ M+P+1

9.To avoid delay from each FA of a Parallel adder, instead which adder is used?
(a) CLA adder (b) Adder/Subtractor (c) BCD Adder (d) Excess-3 Adder

10. Minimized expression for given k-map is_____

(a) 0 (b) x (c) cannot be determined (d) 1

11.Quine-McCluskey method is also called as ___________
(a) K-Map (b) Maximization Method
(c) Tabular Method (d) Boolean Method

12.How many adjacent 1's can be grouped in k-map? ______
(a) power of 2 (b) Even (c) Odd (d) any

13.f(a, b) = Σ m (0,1,2) + d(3); minimized f = ___
(a) 0 (b) 1 (c) not possible (d) None

14. Gate used make an Adder IC into an Adder or Subtractor is _______
(a) Ex-OR (b) NOR (c) NAND (d) NOT

15.In an excess-3 adder, if carry generated after addition of 4-bits, then correction is done by adding ______
(a) 0110 (b) 1100 (c) 0011 (d) 1101

16.In a BCD adder, if carry generated after addition of 4-bits, then correction is done by adding ______
(a) 0110 (b) 1101 (c) 0011 (d) 1100

17.4x1 Mux has ___________number of selection lines
(a) 1 (b) 2 (c) 3 (d) 4

18.To implement a 16x1 Mux using 4x1Mux(s), Minimum number of 4x1Mux(s) required are __
(a) 4 (b) 5 (c) 6 (d) 7

19.If nput to a priority encoder is, abcd=0110. Output of the priority encoder is AB=
Let a=msb and d= lsb; A=msb, B =lsb;
(a) 10 (b) 00 (c) 11 (d) 01

20.A general Decoder has four input lines; No. of output lines =
(a) 4 (b) 8 (c) 16 (d) 32

Set-A: CABBDABBAD-CABACABBAC

Set-B: CABBDABBAD-CCBADABBAC

Mid-2 KEY

Subjective Part-B:
1. What is PLD? Compare any two PLDs. Implement the functions f(A,B,C,D)= ∑(0,1,2,3,5,7,13,15) and g(A,B,C,D)= ∑(0,1,2,3,4,6,12,14) using 3-input,2-output PLA.
Scheme:
• PLD=1M
• Any two Comparison=1M
• PLA programming table =2M
• Realization=1M
Solution:
Programmable Logic Devices are Logic equipment, where the functionality of the device can be altered using programmable fuses. Hence the name.
PROM:
* Programmable OR logic only
* Fixed AND logic (PROM contains decoder which has fixed AND logic)
* Easy to program the device (Just PROM programming table required)
PAL:
* Programmable AND logic only
* Fixed OR logic (PAL is described as n-wide logic; this n-wide logic is the fixed OR logic at outputs)
* Moderate to design, as OR gates are already fused; (PAL programming table required)
PLA:
* Both AND logic and OR logic are programmable.
* There is no fixed logic
* Difficult to design (as both logics are programmable, Ture and Complement functions must be obtained carefully)

PLA design for given problem:
Step1: K-maps for reducing Product Terms (PT). That is why both f(T) and f(C) are both obtained. Similarly in case of function g, g(T) and g(C) also.

Now comparing common terms in True and Complement functions:
• f(T) and g(T); this produces THREE Terms i.e., A'B'(common), BD, BD'
• f(T) and g(C); this produces THREE Terms i.e., A'B', BD (common), AB'
• f(C) and g(T); this produces THREE Terms i.e., AB', BD'(common), A'B'
• f(C) and g(C); this produces THREE Terms i.e., AB'(common), BD', BD

Here all the combinations produce three PT; So, any of the above combination can be used ; I choose f(T) and g(C). So the product terms will be A’B’, BD, AB’. [BD is product term covered commonly by both the f(T) and g(C);]
Step2:
PLA Programming table is:

Step3: Realization using PLA

--------------

2. Convert S-R flipflop to J-K Flipflop.
Scheme:
• Conversion steps=2M
• K-Maps=2M
• Realization=1M
Solution:
Step1: Fill Qn+1;

Step2:

Step3: Fill S,R values based on Qn, Qn+1 (i.e. SR-FF excitation table)

Final table is:

Step4: Now Draw k-maps, obtain equations for ‘S’, ‘R’:

Step5: Realization

--------------

3. Analyse the below circuit, obtain its state diagram.

Scheme:
• Equations =2M
• State table=2M
• State diagram=1M
Solution:
Step1:
The equations representing the excitations are:
T2= x
T1= Q2 x
The equations representing the output is:
z=Q2 Q1

Step2: Draw the modified state table; Here NS= ??

Fill the values of T2, T1, z based on PS, x values.

Step3: Now based on characteristic equation of T-FF, Fill the NS.
T-FF characteristic equation is Qn+1 = TQ’ +T’Q =T⊕Q
For example: NS --> Q2 = T2Q2’ + T2’Q2
If Q2=0, T2=0 --> NS(Q2) = 0⊕0 = 0; similarly fill all the table NS values.

Step4: Now draw the state table from the modified state table.

Step5: Draw the State diagram for above state table.

--------------

Objective Key:

1.PLA is an example of _________

(a) FPGA

(b) PROM

(d) PLD

2.Number of inputs for a 256x3 PROM
(a) 6
(b) 7
(c) 8
(d) 9
(e) 3

3. Functions f(a,b) and g(a,b) are implemented in a PLD, as f(T) and g(C); PLD is__
(a) PAL
(b) PLA
(c) PROM
(d) None

4.PAL has ____ Fixed logic and ____ programmable logic.
(a) OR, AND
(b) AND, Ex-OR
(c) AND, OR
(d) Ex-OR, AND

5. Characteristic Equation for JK-FF: Qn+1 =
(a) JQ’+K’Q
(b) JQ’+KQ
(c) JQ+K’Q
(d) JQ+KQ

6. If Qn=1, Qn+1 = 0; Then J = __, K= ___
(a) x,0
(b) x,1
(c) 1,x
(d) 0,x

7. No. of states in a ring counter: ____
(a) 8
(b) 6
(c) 4
(d) 2
(e) 1

8. Johnson’s Counter also called as _______ counter
(a) Twitted Ring
(b) Tweeted Ring
(c) Treated Ring
(d) Twisted Ring

9. A FF stores ___ number of bit(s).
(a) 2
(b) 3
(c) 0
(d) 1

10.Below is a _______

(a) Shift Register
(b) Ring Counter
(c) Ripple Up counter
(d) Master Slave FF

11.If data moves through FFs from left to right, then that is a __________.
(a) Left Shift Register
(b) Right Shift Register
(c) PIPO Register
(d) All the options are correct.

12. Mod-8 down counter counts from _____ to _____.
(a) 15,8
(b) 15,7
(c) 0,7
(d) 0,8

13. To implement a sequence detector using Moore machine (compared to Mealy machine) requires _________ states.
(a) same/ more
(b) same/less
(c) same
(d) less

14. FSM =
(a) Fine State Mapping
(b) Finite State Machine
(c) Fine State Machine
(d) Finite State Mapping

15. In figure-2 given below, the machine is a ________
(a) Simple
(b) Moore
(c) Mealy
(d) Complex

16. In figure-2 given below, the machine is a _________.
(a) 001 sequence detector
(b) 100 sequence detector
(c) 010 sequence detector
(d) 101 sequence detector
(e) not a sequence detector

17. In figure-2 given below, 1/0 means ______
(a) 1= output, 0= input
(b) 1= output, 0= output
(c) 1= input, 0= input
(d) 1= input, 0= output
(e) 1,0 is error detected

18. In figure-2 given below, no. of states = ______
(a) 1
(b) 2
(c) 3
(d) 4

19. In figure-2 given below, Let PS=S2; at x=1, y= ?
(a) 0
(b) 1
(c) S0
(d) S2

20. In figure-2 given below, is it a sequence detector? Y/N; If Yes, what is overlapping in its case?
(a) Yes, allows Overlapping
(b) Yes, Non-overlapping
(c) No
(d) None

figure-2:

Objective Set-A Key: DCBA ABCD DC-BA ABCD DCBA
Objective Set-B Key: DCBA ABCD EC-BA ABCD DCBA

Sem KEY

TO UPDATE

Practice Questions Unit-wise

STLD Practice Questions:

Chapter-1:

Note: ( )10 : here 10 means base_10 i.e. decimal

1. a) Convert (23.11)10= (_____)2

b) Convert (23.11)10= (_____)8

c) Convert (23.11)10= (_____)16

2. a) Convert (11010111.1011)2= (_____)8

b) Convert (11010111.1011)2= (_____)16

c) Convert (11010111.1011)2= (_____)10

3. (a) (29)10 -(13)10 = ? Solve using 9's complement .

(b) (32-18)10=? Solve using signed 8 bit representation.

4. Realize the following as per the requirement:

(a)Realize both the functions f and g as a single entity; f(a,b,c) = abc+a'b'+c' ; g(a,b,c)= a'c+ac'+bc

(b) g(x,y,z) = x'y+xz'+xy; Realize using NAND-NAND logic

5. Mention all (i) Boolean Postulates

(ii) Boolean theorems

6. Draw the logic symbol, also Mention the Equation, along with truth table for:

(a) NAND Gate

(b) NOR Gate

(d) NOT Gate

7. Express the equations in Canonical form:

(a) f(A,B,C)= AB+AC

(b) g(A,B,C)= (A+B). (A+C)

8. Generate Hamming code for 1011 (left most is MSB)

Chapter-2:

1. Minimize f(a,b,c) = ab+ a'c+ bc using Boolean theorems.

2. Minimize g(A,B,C,D,E)=Σm(0,1,3,5,6,8,10,14,15,16,17,19,31) using K-Map.

3. Minimize h(A,B,C,D) =Σm(1,2,3,5,6,7,8,9,12,13,15) using Tabular method.

4. Explain about 4-bit Adder/subtractor.

5. Illustrate with an example, the working of 4bit BCD Adder

6. Illustrate the working of an Excess-3 adder with an example.

7. convert Excess-3 to Gray and realize the same.

8. Explain about the working of a CLA.

Chapter-3_1:

1. Realize 32x1 Mux using 4x1Mux.

2. Implement f(A,B,C)= AB+BC+AC using 3x8 decoder.

3. Implement g(x,y,z,p)=Σm(0,1,2,5,6,8,9,10,13,15) using 8x1 Mux.

4. (a)Explain about 4bit priority encoder.

(b) With neat logic diagram and truth table, explain the working of 4-bit digital comparator.

Chapter-3_2:

5. Compare PROM, PLA and PAL.

6. Implement f(A,B,C)=Σm(1,2,4,6,7) using 8x2 PROM

7. Implement f(a,b,c,d)=Σm(1,4,6,8,11,14) and g(a,b,c,d) =πM(0,2,3,5,7,9,12,14) using PLA

8. Implement f(A,B,C)=Σm(2,3,5,7) and g(A,B,C)=Σm(0,1,2,3,6) using 4-wide PAL

Chapter-4:

1. With logic symbol, logic diagram, truth table and waveforms explain the working of:

(a) S-R Latch

(b) positive edge triggered JK FF

2. Convert the following:

(a) S-R FF to D-FF

(b) JK FF to SR FF

3. Design a mod-7 ripple up counter.

4. With neat logic diagram, truth table and state diagram, design a 4bit synchronous down counter

5. Explain the following:

(a) Ring counter

(b) Twisted-ring counter

6. Explain the bidirectional shift register

7. Explain the process of loading, shifting (both left and right) using a single 4-bit register

8. Write the excitation tables of

(i) JK FF (ii) D FF (iii) T-FF (iv) SR FF

Chapter-5:

1. Compare Mealy and Moore machines

2. Reduce the state table for the given state diagram using state reduction technique.

3.For the below given model, obtain the state table and state diagram.

4. Implement the below using JK FF.

5. Implement the below state table by considering unused states.

6. Design a sequence detector to detect 1010 in the input sequence. (without overlapping)

7. Design a sequence detector to detect 1010 in the input sequence. (with overlapping)

8. Design a 10 sequence detector. (Non-overlapping Mealy)

×-×-×-×-×-×-×-×-×-×-×-×-×-×-×-×-×-×-

STLD Lab

STLD Lab

Experiment-1: Verification of functionality of logic gates

Various ICs used in Lab are:

NAND:

7400- 2 i/p - x4 gates

7410- 3 i/p - x3 gates

7420- 4 i/p - x2 gates

7430- 8 i/p - x1 gate

NOR:

7402-- 2 i/p - x4 gates

AND:

7408-- 2 i/p - x4 gates

7411-- 3 i/p - x3 gates

7421-- 4 i/p - x2 gates

OR:

7432-- 2 i/p - x4 gates

NOT:

7404-- - x6 gates

(a) OR gate:

Expression:

Y =A+B

Truth Table:

A B Y

0 0 0

0 1 1

1 0 1

1 1 1

(b) AND gate:

Expression:

Y =A.B

Truth Table:

A B Y

0 0 0

0 1 0

1 0 0

1 1 1

Expression:

Y =A'

Truth Table:

A Y

0 1

1 0

(d) NOR gate:

Expression:

Y =(A+B)' = A' . B'

Truth Table:

A B Y

0 0 1

0 1 0

1 0 0

1 1 0

(e) NAND gate:

Expression:

Y = (A.B)' = A' + B'

Truth Table:

A B Y

0 0 1

0 1 1

1 0 1

1 1 0

(f) ExOR gate:

Expression:

Y =A ⨁ B = A'B + AB'

Truth Table:

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

(g) ExNOR gate:

Expression:

Y = A⨀B = (A ⨁ B)' = A'B' + AB

Truth Table:

A B Y

0 0 0

0 1 1

1 0 1

1 1 0

Expreriment-2: Implement and Verify the functionality of a three variable minimal SOP.

A, B, C are inputs; Y is output.

Let the truth table be as shown.

A B C Y

0 0 0 1

0 0 1 1

0 1 0 1

0 1 1 1

1 0 0 0

1 0 1 0

1 1 0 1

1 1 1 0

Y = A'+BC'

Realize the above function using basic gates. The gates required here are:

NOT gate =2

OR gate =1

AND gate =1

Now verify the truth table inputs and outputs for the logic connections given in the kit.

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